1. Field of the Invention
The present invention relates to a stackable semiconductor package, more particularly to a stackable semiconductor package having a supporting element.
2. Description of the Related Art
FIG. 1 is a schematic sectional view of a conventional stackable semiconductor package. The conventional stackable semiconductor package 1 comprises a first substrate 11, a chip 12, a second substrate 13, a plurality of wires 14, and a molding compound 15. The first substrate 11 has a first surface 111 and a second surface 112. The chip 12 is attached to the first surface 111 of the first substrate 11 by means of a flip chip. The second substrate 13 is adhered to the chip 12 by the use of an adhesive layer 16, and has a first surface 131 and a second surface 132, wherein the first surface 131 has a plurality of first pads 133 and a plurality of second pads 134 disposed thereon. From a top view, the area of the second substrate 13 is larger than that of the chip 12, such that the second substrate 13 partially extends beyond the chip 12, thus forming an overhang portion.
The wires 14 electrically connect the first pads 133 of the second substrate 13 to the first surface 111 of the first substrate 11. The molding compound 15 encapsulates the first surface 111 of the first substrate 11, the chip 12, the wires 14, and a portion of the second substrate 13, and the second pads 134 on the first surface 131 of the second substrate 13 are exposed outside the molding compound 15, thereby forming a mold area opening 17. Under ordinary circumstances, the conventional stackable semiconductor package 1 further comprises another package 18 or other devices stacked at the mold area opening 17, wherein solder balls 181 of the package 18 are electrically connected to the second pads 134 of the second substrate 13.
The disadvantages of the conventional stackable semiconductor package 1 are described as follows. First, as the second substrate 13 has an overhang portion, the first pads 133 are disposed in the periphery of the corresponding position (i.e., the overhang portion) of the chip 12. The distance between the corresponding position of the first pads 133 and the edge of the chip 12 is defined as an overhang length L1. Experimental results show that during the wire bonding process, when the overhang length L1 is more than three times larger than the thickness T1 of the second substrate 13, the overhang portion may shake or sway, which is disadvantageous for the wire bonding process. Further, during the wire bonding process, when the second substrate 13 is subjected to an excessive downward stress, the second substrate 13 may be cracked. Then, due to the above sway, shake or crack, the overhang portion cannot be too long, or it would limit the area of the second substrate 13, thus further limiting the layout space of the second pads 134 on the first surface 131 of the second substrate 13 exposed by the mold area opening 17. Finally, in order to overcome the above sway, shake or crack, the second substrate 13 cannot be too thin, such that the overall thickness of the conventional stackable semiconductor package 1 cannot be effectively reduced.
Therefore, it is necessary to provide a stackable semiconductor package having a supporting element to solve the above problems.